The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. CMOS devices have typically been formed with a gate oxide and polysilicon gate electrode. There has been a desire to replace the gate oxide and polysilicon gate electrode with a high-k gate dielectric and metal gate electrode to improve device performance as feature sizes continue to decrease. However, problems arise when integrating a high-k/metal gate feature in a CMOS process flow due to various factors such as incompatibility of materials, complex processes, and thermal budgets. For example, one issue for high-k gate dielectric is its lower thermal stability. Accordingly, the high-k gate dielectric quality may change and degrade during one or more thermal process cycles (e.g., dummy poly thermal, SiGe or spacer thermal, and source and drain activation) in the CMOS process flow. Further, patterning the metal layers with a photoresist may induce photoresist peeling, photoresist residue after stripping, and encroachment of the metal etching chemical through the photoresist.